1. Field of the Invention
The present invention relates to a metal-oxide semiconductor (MOS) transistor and manufacturing methods thereof, and more particularly, to a MOS transistor and manufacturing methods thereof utilizing selective epitaxial growth (SEG) method.
2. Description of the Prior Art
Selective epitaxial growth (SEG) technology is used to form an epitaxial silicon layer on a single-crystalline substrate, in which the crystalline orientation of the epitaxial silicon layer is almost identical to that of the substrate. SEG technology is widely applied in manufacturing numerous kinds of semiconductor devices, such as MOS transistors having raised source/drain regions which benefits from good short channel character and low parasitical resistance and a MOS transistor having recessed source/drain which improves drain induced barrier lowering (DIBL) and punchthrough effect and reduces off-state current leakage and power consumption.
Generally, SEG technology includes performing a cleaning process to remove native oxides and other impurities from a surface of a substrate, then depositing an epitaxial silicon layer on the substrate and making the epitaxial silicon layer grow along with the silicon lattice of the substrate. Please refer to FIGS. 1-4, which are drawings illustrating a conventional method for manufacturing a MOS transistor utilizing SEG technology. As shown in FIG. 1, a substrate 100, such as a silicon substrate, is provided. The substrate 100 comprises a gate structure 110 having a gate dielectric layer 112, a gate conductive layer 114 formed on the gate dielectric layer 112, a hard mask layer 116 formed on the gate conductive layer 114 for defining and protecting the gate conductive layer 114, lightly doped drains (LDDs) 118 formed in the substrate 100 on two sides of the gate conductive layer 114, and a spacer 120 formed on sidewalls of the gate conductive layer 114. Additionally, active areas where the gate structure 110 is positioned are electrically isolated from each other by a shallow trench isolations (STIs) 130.
Please refer to FIG. 2. A patterned cap layer 140 is formed on the substrate 100 acting as a mask in an etching process. Then an isotropic dry etching process is performed to form recesses 150 in the substrate 100 where the patterned cap layer 140 does not cover. Please refer to FIG. 3. After a cleaning process used to remove native oxides and other impurities is performed, a SEG process is performed by filling the recesses 150 with an epitaxial silicon layer 152, such as a silicon germanium (SiGe) layer, to form a source/drain of a PMOS transistor.
Please refer to FIG. 3 again. The epitaxial silicon layer 152 grows along the silicon surface of the substrate 100 in the recess 150 and is in an identical orientation with the silicon lattice of the substrate 100. For example, the epitaxial silicon layer 152 grows along the arrow shown in FIG. 3. However, the STI 130 is filled with silicon oxide material, therefore a seam 154 is formed in between the epitaxial silicon layer 152 and the STI 130 after the SEG process. It is noteworthy that since many processes will be performed to clean the substrate 100 and to remove the hard mask layer 140 and the cap layer 116 after forming the epitaxial silicon layer 152, the seam 154 will successively grow larger and deeper into the epitaxial silicon layer 152, even exposing the substrate 100.
Please refer to FIG. 4. In the following process such as a self-align silicidation (Salicide) process, a metal layer (not shown) sputtered on the substrate 100 will react with silicon atom of the substrate 100 and result in a salicide layer 160. The existence of the seam 154 makes the silicon atoms of the epitaxial silicon layer 152 consumed by the metal layer excessively, and even exposes the substrate 100 to the metal layer. Therefore the salicide layer 160 may form under the STI 130 and cause current leakage.